Hardware components, such as processors, may dynamically alter their frequency to balance performance and power consumption. Running at a lower frequency may reduce power consumption at a cost to performance, while running at a higher frequency may increase performance but consume more power. The ability to dynamically scale processor clock frequency and power supply voltage with workload is a useful technique for reducing active and standby power consumption in nanoscale embedded systems and other applications. This dynamic adjustment is commonly known as Dynamic Frequency Scaling (DFS) or Dynamic Voltage Frequency Scaling (DVFS).
DVFS has been used successfully to reduce power in many applications, such as portable embedded applications (e.g., PDAs and cell phones) and other applications. DVFS circuits may be implemented with a phase-lock loop (PLL) that may be used to multiply a low frequency reference signal that is typically derived from an external crystal oscillator. A PLL prescaler can be changed to generate a new clock frequency to dynamical scale the processor clock frequency.